Nonvolatile memory technologies such as NAND flash memory devices have been generating increased market revenue due to the increased usage of these devices, especially in portable consumer electronics and solid state drives (SSDs). The trend toward cloud storage and computing is continuously demanding that enterprises invest especially in SSD-based storage architectures, as these provide higher performance compared to hard disk drives (HDDs).
Flash memories have been providing solutions to the ever-increasing high-performance storage demands with continued feature scaling. However, flash scaling is reaching its limits due to the increased reliability problems, such as, for example, the aging of the oxide used in such devices, charge leakage, retention problems, and the increased capacitive coupling between floating gates of neighboring cells. The approaching end of flash scaling has resulted in research into alternative nonvolatile memory technologies that can sustain the scaling trend. Many promising emerging technologies have been proposed, each with its own advantages and challenges. These include, for example, the following architecture: magnetoresistive random access memory (MRAM); spin-transfer torque random access memory (STT-RAM); and phase change random access memory (PCRAM) devices.
Of particular interest, however, is the resistive random access memory (RRAM) architecture which may be embodied in a resistive crossbar memory structure. Crossbar memory structures provide increased resistive memory cell density as compared to other architectures, as well as both single and multi-bit per cell storage capabilities. Crossbar memory architectures/structures are not without their drawbacks, however.
For example, various write schemes have been proposed for writing to the resistive memory elements or cells of a crossbar memory structure. One such scheme is a pulse-based scheme in which a pulse having predetermined amplitude is applied to the memory cell of interest for a predetermined duration. Another scheme is a feedback-based scheme in which a pulse having a predetermined amplitude is applied to the cell of interest for a duration that is dependent upon the output of a feedback circuit indicating that the cell has reached a desired resistive state (e.g., “01,” “10,” or “11”). While conventional feedback-based schemes have been shown to have advantages over conventional pulsed-based schemes, use of DAC, ADC, and/or multi-stage comparisons in the feedback circuitry can introduce significant peripheral circuitry overhead and can introduce latency in response time that can be significant when the memory structure is highly non-linear. Additionally, as will be appreciated by those having ordinary skill in the art, memory cells of the crossbar memory may experience a phenomenon known in the art as “resistance drift” caused, for example, by read/write disturbances in the array and sneak paths between cells in the array. Due to resistance drift, the programmed resistance value of a cell for a given state may change over time, and thus, different resistance values may be stored in different cells for the same state.
Accordingly, there is a need for crossbar memory structures and/or components thereof that minimize and/or eliminate one or more of the above-identified deficiencies or drawbacks, and/or decreases the complexity and latency in the circuitry of the structure and/or the read/write methodology while operating at CMOS compatible voltages.